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NEW QUESTION: 1
Which of the following is true about the early exercise of an American call option:
A. An early exercise of an American call option may be justified if an extraordinarily large dividend payment is imminent
B. An early exercise of an American call option is never a good idea as an option is always worth more alive than when it is dead
C. An early exercise of an American call option is advisable whenever the option is deep in the money and delta approaches 1
D. An early exercise of an American option, if ever to be done, should be done immediately after an ex-dividend date
Answer: A
Explanation:
Explanation
Generally, it is not a good idea to exercise an option early as any more upside in the remaining period to expiry is being sacrificed. However, if an extraordinarily large dividend is coming due, and this dividend is larger than the interest foregone from holding the option, it may be a good idea to exercise the option early. In such cases, the exercise needs to happen before the ex-dividend date and not afterwards. Choice 'b' is therefore the correct answer.
Even if the option is deep in the money and delta is approaching 1, and exercise upon maturity is almost a certainty, it would still always be better to sell the option than exercise it . Therefore Choice 'a' is incorrect.
Choice 'c' is correct in all cases except when a large dividend is coming in. Choice 'd' is not correct because an early exercise needs to happen prior to the ex-dividend date and not afterwards.
NEW QUESTION: 2
-- Exhibit-
-- Exhibit -
Refer to the exhibits.
When observing the AVR statistics for the HTTPS_VS, an LTM Specialist realizes that HTTP status codes are NOT being recorded.
How should the LTM Specialist modify the configuration to record the HTTP status codes?
A. assign client SSL and server SSL profiles to the virtual server
B. enable Collected Entities, Response Codes on the analytics profile
C. assign a streaming profile to the virtual server
D. enable Statistics Logging Type, External on the analytics profile
Answer: B
NEW QUESTION: 3
Which of the following describes a computer processing architecture in which a language compiler or pre-processor breaks program instructions down into basic operations that can be performed by the processor at the same time?
A. Complex-Instruction-Set-Computer (CISC)
B. Very-Long Instruction-Word Processor (VLIW)
C. Super Scalar Processor Architecture (SCPA)
D. Reduced-Instruction-Set-Computer (RISC)
Answer: B
Explanation:
Very long instruction word (VLIW) describes a computer processing architecture in which a language compiler or pre-processor breaks program instruction down into basic operations that can be performed by the processor in parallel (that is, at the same time). These operations are put into a very long instruction word which the processor can then take apart without further analysis, handing each operation to an appropriate functional unit.
The following answer are incorrect:
The term "CISC" (complex instruction set computer or computing) refers to computers designed with a full set of computer instructions that were intended to provide needed capabilities in the most efficient way. Later, it was discovered that, by reducing the full set to only the most frequently used instructions, the computer would get more work done in a shorter amount of time for most applications. Intel's Pentium microprocessors are CISC microprocessors.
The PowerPC microprocessor, used in IBM's RISC System/6000 workstation and Macintosh computers, is a RISC microprocessor. RISC takes each of the longer, more complex instructions from a CISC design and reduces it to multiple instructions that are shorter and faster to process. RISC technology has been a staple of mobile devices for decades, but it is now finally poised to take on a serious role in data center servers and server virtualization. The latest RISC processors support virtualization and will change the way computing resources scale to meet workload demands.
A superscalar CPU architecture implements a form of parallelism called instruction level parallelism within a single processor. It therefore allows faster CPU throughput than would otherwise be possible at a given clock rate. A superscalar processor executes more than one instruction during a clock cycle by simultaneously dispatching multiple instructions to redundant functional units on the processor. Each functional unit is not a separate CPU core but an execution resource within a single CPU such as an arithmetic logic unit, a bit shifter, or a multiplier.
Reference(s) Used for this question:
http://whatis.techtarget.com/definition/0,,sid9_gci214395,00.html and http://searchcio-midmarket.techtarget.com/definition/CISC and http://en.wikipedia.org/wiki/Superscalar
NEW QUESTION: 4
Based on the following request, select the most appropriate command for creating a database cluster. ?Character encoding of the template database needs to be EUC_JP ?Locale is not used
A. pg_ctl init --encoding=EUC_JP
B. initdb --encoding=EUC_JP --no-locale
C. initdb --locale=EUC_JP --no-encoding
D. initdb --default-encoding=EUC_JP
E. pg_ctl init --locale=EUC_JP
Answer: B
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