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NEW QUESTION: 1
In a vSphere Distributed Switch architecture, which plane handles packet switching?
A. Management Plane
B. Data Plane
C. Forwarding Plane
D. Control Plane
Answer: B
Explanation:
Explanation/Reference:
Reference: https://www.slideshare.net/VMworld/vmworld-2013-vsphere-distributed-switch-design-and- best-practices (slide 7)
NEW QUESTION: 2
An employee authenticates using their corporate laptop and runs the dissolvable onguard agent to send a health check back the Policy Manager. Based on the health of the device a VLAN is assigned to the corporate laptop.
Which licenses are consumed in this scenario?
A. 2 Policy Manager licenses, 2 Onguard licenses.
B. 2 Policy Manager licenses, 1 OnGuard License.
C. 1 Policy Manager license, 1 OnGuard License.
D. 1 Policy Manager license, 1 Profile License.
E. 1 Policy Manager license, 1 Onboard License.
Answer: C
NEW QUESTION: 3
The definition A relatively small amount (when compared to primary memory) of very high speed RAM, which holds the instructions and data from primary memory, that has a high probability of being accessed during the currently executing portion of a program refers to what category of computer memory?
A. Virtual
B. Cache
C. Real
D. Secondary
Answer: B
Explanation:
Cache logic attempts to predict which instructions and data in main (primary) memory will be used by a currently executing program. It then moves these items to the higher speed cache in anticipation of the CPU requiring these programs and data. Properly designed caches can significantly reduce the apparent main memory access time and thus increase the speed of program execution.
*Answer secondary memory is a slower memory (such as a magnetic disk) that provides non-volatile storage.
*Real or primary memory is directly addressable by the CPU and is used for the storage of instructions and data associated with the program that is being executed. This memory is usually high-speed, Random Access Memory (RAM).
*Answer virtual memory uses secondary memory in conjunction with primary memory to present the CPU with a larger, apparent address space of the real memory locations.
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